RESEARCH ARTICLES
SCoPE: Statistical Regression Based Power Models for Co-Processors Power Estimation
Sumit Ahuja, Deepak A. Mathaikutty, Avinash Lakshminarayana, and Sandeep K. Shukla
J. Low Power Electron. 5, 407–415 (2009)
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Energy and Power Consumption Estimation for Embedded Applications and Operating Systems
Saadia Dhouib, Eric Senn, Jean-Philippe Diguet, Dominique Blouin, and Johann Laurent
J. Low Power Electron. 5, 416–428 (2009)
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Novel SAT-Based Peak Dynamic Power Estimation for Digital Circuits
K. Shyamala, J. Vimalkumar, and V. Kamakoti
J. Low Power Electron. 5, 429–438 (2009)
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Energy-Aware Compilation for Embedded Processors with Technology Scaling Considerations
Po-Kuan Huang and Soheil Ghiasi
J. Low Power Electron. 5, 439–453 (2009)
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An Optimal Resource Binding Algorithm with Inter-Transition Switching Activities for Low Power
Deming Chen and Scott Cromar
J. Low Power Electron. 5, 454–463 (2009)
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State Assignment and Polarity Selection for Low Dynamic Power and Testable Finite State Machine Synthesis
Saurabh Chaudhury, J. Srinivas Rao, and Santanu Chattopadhyay
J. Low Power Electron. 5, 464–473 (2009)
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A New Cell Design Methodology for Balanced XOR–XNOR Circuits for Hybrid-CMOS Logic
Tooraj Nikoubin, Fatemeh Eslami, Amirali Baniasadi, and Keivan Navi
J. Low Power Electron. 5, 474–483 (2009)
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Performance Analysis of Subthreshold Cascode Current Mirror in 130 nm CMOS Technology
Balaji Jayaraman and Navakanta Bhat
J. Low Power Electron. 5, 484–496 (2009)
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Robust FinFET Memory Circuits with P-Type Data Access Transistors for Higher Integration Density
and Reduced Leakage Power
Sherif A. Tawfik and Volkan Kursun
J. Low Power Electron.5, 497–508 (2009)
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An Asynchronous Sigma Delta Analog to Digital Converter for Broadband Wireless Receiver with
Adaptive Digital Filtering Technique
Simon Sheung Yan Ng and Steve B. Bibyk
J. Low Power Electron. 5, 509–519 (2009)
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Automatic Handling of Programmable On-Product Clock Generation (OPCG) Circuitry for
Low Power Aware Delay Test
Anis Uzzaman, Brion Keller, Tom Snethen, Kazuhiko Iwasaki, and Masayuki Arai
J. Low Power Electron. 5, 520–528 (2009)
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Table of Contents to Volume 5, Number 1–4, 2009
J. Low Power Electron. 5, 529–531 (2009)
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Author Index to Volume 5, Number 1–4, 2009
J. Low Power Electron. 5, 532–535 (2009)
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Subject Index to Volume 5, Number 1–4, 2009
J. Low Power Electron. 5, 536–538 (2009)
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A SPECIAL ISSUE
22nd IEEE International Conference on VLSI Design’’ New Delhi, India, 5–9 January 2009
Guest Editors: Rajendran Panda and Preeti Ranjan Panda
J. Low Power Electronics 5, 255–256 (2009)
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RESEARCH ARTICLES
CMOS Proportional-to-Absolute Temperature Current Reference for Low Voltage Operation
Sanjay Kumar Wadhwa
J. Low Power Electronics 5, 257–264 (2009)
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Switched-Capacitor Based Buck Converter Design Using Current Limiter
Tamal Das and Pradip Mandal
J. Low Power Electronics 5, 265–278 (2009)
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A Novel Low Power, Variable Resolution Flash Analog-to-Digital Converter
A. Mahesh Kumar, Sreehari Veeramachaneni, and M. B. Srinivas
J. Low Power Electronics 5, 279–290 (2009)
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Automatic Design of Low-Power Low-Voltage Analog Circuits Using Particle Swarm Optimization with
Re-Initialization
Rajesh A. Thakker, M. Shojaei Baghini, and M. B. Patil
J. Low Power Electronics 5, 291–302 (2009)
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Low-Power VLSI Design of LDPC Decoder Using Dynamic Voltage and Frequency Scaling for
Additive White Gaussian Noise Channels
Weihuang Wang, Euncheol Kim, Kiran K. Gunnam, and Gwan S. Choi
J. Low Power Electronics 5, 303–312 (2009)
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Environment and Process Adaptive Low Power Wireless Baseband Signal Processing Using
Dual Real-Time Feedback
Muhammad M. Nisar and Abhijit Chatterjee
J. Low Power Electronics 5, 313–325 (2009)
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Design and Evaluation of an Energy-Delay-Area Efficient Datapath for Coarse-Grain Reconfigurable
Computing Systems
Sohan Purohit, Marco Lanuzza, Stefania Perri, Pasquale Corsonello, and Martin Margala
J. Low Power Electronics 5, 326–338 (2009)
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Dedicated Rewriting: Automatic Verification of Low Power Transformations in Register Transfer Level
Vinod Viswanath, Shobha Vasudevan, and Jacob A. Abraham
J. Low Power Electronics 5, 339–353 (2009)
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Metric Based Multi-Timescale Control for Reducing Power in Embedded Systems
Nitin Kataria, Forrest Brewer, João Hespanha, and Timothy Sherwood
J. Low Power Electronics 5, 354–362 (2009)
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Temperature Aware Scheduling for Embedded Processors
Ramkumar Jayaseelan and Tulika Mitra
J. Low Power Electronics 5, 363–372 (2009)
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A General Approach to High-Level Energy and Performance Estimation in System-on-Chip Architectures
Sandro Penolazzi, Ahmed Hemani, and Luca Bolognino
J. Low Power Electronics 5, 373–384 (2009)
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Forecasting-Based Dynamic Virtual Channel Management for Power Reduction in Network-on-Chips
Amir-Mohammad Rahmani, Masoud Daneshtalab, Ali Afzali-Kusha, and Massoud Pedram
J. Low Power Electronics 5, 385–395 (2009)
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A Novel Synthetic Traffic Pattern for Power/Performance Analysis of Network-on-Chips Using Negative Exponential Distribution
Amir-Mohammad Rahmani, Ali Afzali-Kusha, and Massoud Pedram
J. Low Power Electronics 5, 396–405 (2009)
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RESEARCH ARTICLES
A Novel Low Energy Scheduling Algorithm for Clustered Very Long Instruction Word Architectures
Yang Xu, He Hu, and Sun Yihe
J. Low Power Electronics 5, 123–134 (2009)
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A Formally Verified Peak-Power Reduction Technique for Hardware Synthesis from Concurrent
Action-Oriented Specifications
Gaurav Singh, Jacob B. Schwartz, and Sandeep K. Shukla
J. Low Power Electronics 5, 135–144 (2009)
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Soft Error-Aware Voltage Scaling Technique for Power Minimization in Application-Specific
Multiprocessor System-on-Chip
Rishad Ahmed Shafik, Bashir M. Al-Hashimi, Sandip Kundu, and Alireza Ejlali
J. Low Power Electronics 5, 145–156 (2009)
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Encoding Serial Graphical Data for Energy-Delay Product/Energy Minimization
Sasidharan Ekambavanan, Rajesh Garg, Sunil P. Khatri, and Krishna R. Narayanan
J. Low Power Electronics 5, 157–172 (2009)
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A Workload Based Lookup Table for Minimal Power Operation Under Supply and Body Bias Control
K. Sreejith, Bharadwaj Amrutur, and Ashok Balivada
J. Low Power Electronics 5, 173–184 (2009)
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Selective Forward Body Bias for High Speed and Low Power SRAMs
Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, and Sunil P. Khatri
J. Low Power Electronics 5, 185–195 (2009)
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A Design Technique for Power Constrained CMOS Low-Noise Amplifier Dedicated to Wireless
Sensor Networks
Guillaume Terrasson, Renaud Briand, and Skandar Basrour
J. Low Power Electronics 5, 196–205 (2009)
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Noise Minimization for Low Power Bandgap Reference and Low Dropout Regulator Cores
Ângelo Monteiro, Marcelino Santos, Alexandre Neves, and Nuno Dias
J. Low Power Electronics 5, 206–222 (2009)
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A Multi-Stage Low-Dropout Regulator with 1 pF Compensation Capacitor for System-on-Chip
Applications
Wing Yan Leung, Tsz Yin Man, Dongwei Zhang, and Mansun Chan
J. Low Power Electronics 5, 223–228 (2009)
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Achieving High Efficiency Under Micro-Watt Loads with Switching Buck DC–DC Converters
Suhwan Kim and Gabriel A. Rincón-Mora
J. Low Power Electronics 5, 229–240 (2009)
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Gate Driver Voltage Optimization for Multi-Mode Low Power DC-DC Conversion
Nuno Dias, Marcelino Santos, Ângelo Monteiro, Pedro Braga, and Alexandre Neves
J. Low Power Electronics 5, 241-254 (2009)
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ERRATUM
Adaptive Global Elimination Algorithm for Low Power Motion Estimation
Journal of Low Power Electronics, Vol. 5, pp. 1-16 (2009)
Ajit Gupte and Amrutur Bharadwaj
J. Low Power Electronics 5, (i)-(ii) (2009)
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RESEARCH ARTICLES
Adaptive Global Elimination Algorithm for Low Power Motion Estimation
Ajit Gupte and Amrutur Bharadwaj
J. Low Power Electronics 5, 1–16 (2009)
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A Low Power Design Space Exploration Methodology Based on High Level Models and Confidence Intervals
Jalel Ktari and Mohamed Abid
J. Low Power Electronics 5, 17–30 (2009)
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Design of Low Power Parallel Multiplier
Rahul M. Badghare, Sanjiv Kumar Mangal, Raghavendra B. Deshmukh, and Rajendra M. Patrikar
J. Low Power Electronics 5, 31–39 (2009)
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Design of Low Power Adiabatic SRAM Using DTGAL, CPAL and ACPL: A Comparative Study
Y. K. Sudharshan, D. Sreenu, A. K. Saxena, and S. Dasgupta
J. Low Power Electronics 5, 40–49 (2009)
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Modified Design and Analysis of a Performance Optimized Common Gate LNA for
Low Power Wireless Sensor Network Applications
T. Sasilatha and J. Raja
J. Low Power Electronics 5, 50–57 (2009)
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Test Power Reduction Using Integrated Scan Cell and Test Vector Reordering Techniques on
Linear Scan and Double Tree Scan Architectures
George Kurian, Narayana Rao, Virendra Patidar, V. Kamakoti, and Srivaths Ravi
J. Low Power Electronics 5, 58–68 (2009)
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A SPECIAL SECTION
Selected Peer-Reviewed Articles from the PATMOS 2008 Workshop
Guest Editor: Lars Svensson
J. Low Power Electronics 5, 69 (2009)
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RESEARCH ARTICLES
Statistical Power Analysis for High-Performance Processors
Howard Chen, Scott Neely, Jinjun Xiong, Vladimir Zolotov, and Chandu Visweswariah
J. Low Power Electronics 5, 70–76 (2009)
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Low-Power Coding for Networks-on-Chip with Virtual Channels
Alberto García-Ortiz, Leandro S. Indrusiak, Tudor Murgan, and Manfred Glesner
J. Low Power Electronics 5, 77–84 (2009)
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Low Energy ASIC Elliptic Curve Processor
Maurice Keller and William P. Marnane
J. Low Power Electronics 5, 85–95 (2009)
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Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures
Dmitrij Kissler, Andreas Strawetz, Frank Hannig, and Jürgen Teich
J. Low Power Electronics 5, 96–105 (2009)
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Intelligate: An Algorithm for Learning Boolean Functions for Dynamic Power Reduction
Roni Wiener, Gila Kamhi, and Moshe Y. Vardi
J. Low Power Electronics 5, 106–112 (2009)
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Exploiting Temporal Discharge Current Information to Improve the Efficiency of Clustered Power-Gating
A. Sathanur, L. Benini, A. Macii, E. Macii, and M. Poncino
J. Low Power Electronics 5, 113–121 (2009)
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