A SPECIAL SECTION
A Special Section on the 24th "IEEE International Conference on VLSI Design" Chennai, India, 2-7 January 2011
Guest Editors: Nitin Chandrachoodan and Shankar Balachandran
J. Low Power Electron. 7, 459 (2011)
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RESEARCH ARTICLES
Ultra Low Energy CMOS Logic Using Below-Threshold Dual-Voltage Supply
Kyungseok Kim and Vishwani D. Agrawal
J. Low Power Electron. 7, 460-470 (2011)
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A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level
Leakage Optimization
Shibaji Banerjee, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan, and Maciej J. Ciesielski
J. Low Power Electron. 7, 471-481 (2011)
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A Polynomial Based Approach to Wakeup Time and Energy Estimation in Power-Gated Logic Clusters
Vivek D. Tovinakere, Olivier Sentieys, and Steven Derrien
J. Low Power Electron. 7, 482-489 (2011)
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Trading Accuracy for Power in a Multiplier Architecture
Parag Kulkarni, Puneet Gupta, and Miloš D. Ercegovac
J. Low Power Electron. 7, 490-501 (2011)
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Design Techniques with Multiple Scan Compression CoDecs for Low Power and High Quality Scan Test
Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji, and Srivaths Ravi
J. Low Power Electron. 7, 502-515 (2011)
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Analyzing and Improving Performance and Energy Efficiency of Android
Tapas Kumar Kundu and Kolin Paul
J. Low Power Electron. 7, 516-528 (2011)
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A SPECIAL SECTION
A Special Section on the 12th "IEEE Latin-American Test Workshop" Porto de Galinhas, Brazil, 27-30 March 2011
Guest Editors: Victor Champac, Fernanda Kastensmidt, Letícia Maria Bolzani Poehls, Fabian Vargas, and
Yervant Zorian
J. Low Power Electron. 7, 529-530 (2011)
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RESEARCH ARTICLES
Studying the Influence of Chip Temperatures on Timing Integrity Using Improved Power Modeling
András Timár and Márta Rencz
J. Low Power Electron. 7, 531-540 (2011)
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Inclusion of Power Consumption Information in High-Level Modeling of Linear Analog Blocks
Laurent Bousquet, Fabio Cenni, and Emmanuel Simeu
J. Low Power Electron. 7, 541-551 (2011)
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Power-Efficient Application of Sleep Transistors to Enhance the Reliability of Integrated Circuits
Claas Cornelius, Frank Sill Torres, and Dirk Timmermann
J. Low Power Electron. 7, 552-561 (2011)
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On-Line BIST for Performance Failure Prediction Under NBTI-Induced Aging in Safety-Critical Applications
R. S. Oliveira, J. Semião, I. C. Teixeira, M. B. Santos, and J. P. Teixeira
J. Low Power Electron. 7, 562-572 (2011)
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Test Power Reduction via Deterministic Alignment of Stimulus and Response Bits
Sobeeh Almukhaizim, Eman AlQuraishi, and Ozgur Sinanoglu
J. Low Power Electron. 7, 573-584 (2011)
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Table of Contents to Volume 7, Numbers 1-4, 2011
J. Low Power Electron. 7, 585-587 (2011)
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Author Index to Volume 7, Numbers 1-4, 2011
J. Low Power Electron. 7, 588-592 (2011)
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Subject Index to Volume 7, Numbers 1-4, 2011
J. Low Power Electron. 7, 593-595 (2011)
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RESEARCH ARTICLES
Microprocessor Power Supply Noise Aware Floorplanning Using a Circuit-Architectural Framework
Mandar Padmawar, Sanghamitra Roy, and Koushik Chakraborty
J. Low Power Electron. 7, 303-313 (2011)
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A Flexible Architecture for Finite Field Galois Fields(2^m) Arithmetic Processor
Md Ibrahim Faisal, Zahra Jeddi, Esmaeil Amini, and Magdy Bayoumi
J. Low Power Electron. 7, 314-327 (2011)
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Architecture and Robust Control of a Digital Frequency-Locked Loop for Fine-Grain Dynamic Voltage and
Frequency Scaling in Globally Asynchronous Locally Synchronous Structures
Carolina Albea, Diego Puschini, Pascal Vivet, Ivan Miro-Panades, Edith Beigné, and Suzanne Lesecq
J. Low Power Electron. 7, 328-340 (2011)
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Energy-Efficient Retiming and Scheduling of Datapath-Dominant Digital Systems
Rashmi Nanda and Dejan Markovic
J. Low Power Electron. 7, 341-349 (2011)
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A Specialized Static Content Addressable Memory for Longest Prefix Matching in Internet Protocol Routing
Satendra Kumar Maurya and Lawrence T. Clark
J. Low Power Electron. 7, 350-363 (2011)
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Timing-Driven Power Optimisation and Power-Driven Timing Optimisation of Combinational Circuits
Rashmi Mehrotra, Tom English, Michel Schellekens, Steve Hollands, and Emanuel Popovici
J. Low Power Electron. 7, 364-380 (2011)
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An Efficient Single Phase Adiabatic Logic and Its Application to Combinational and Sequential Design
Jitendra Kanungo and S. Dasgupta
J. Low Power Electron. 7, 381-392 (2011)
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Near-Threshold Computing of Clocked Adiabatic Logic with Complementary Pass-Transistor Logic Circuits
Yangbo Wu and Jianping Hu
J. Low Power Electron. 7, 393-402 (2011)
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Temperature Effects on Practical Energy Optimization of Sub-Threshold Circuits in Deep
Nanometer Technologies
Basab Datta and Wayne Burleson
J. Low Power Electron. 7, 403-419 (2011)
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An Efficient Methodology for Full Chip Signal ElectroMigration Analysis for Advanced Technology Node Designs
Biswajit Patra, Nayan Chandak, and Amlan Chakrabarti
J. Low Power Electron. 7, 420-425 (2011)
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Smart Control of Internal Supply Voltage Spikes in a Low Voltage DC-DC Buck Converter
José F. da Rocha, Marcelino B. dos Santos, and José M. Dores Costa
J. Low Power Electron. 7, 426-443 (2011)
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Studying the Viability of Static Complementary Metal-Oxide-Semiconductor Gates with a Large Number of
Inputs When Using Separate Transistor Wells
D. Guerrero, A. Millan, J. Juan, M. J. Bellido, P. Ruiz-de-Clavijo, E. Ostua, and J. Viejo
J. Low Power Electron. 7, 444-452 (2011)
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A Passive Radio Frequency Amplifier for Radio Frequency Identification Tags
Benjamin S. Mericli, Ajay Ogirala, Peter J. Hawrylak, and Marlin H. Mickle
J. Low Power Electron. 7, 453-458 (2011)
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RESEARCH ARTICLES
Resource Management in Heterogeneous Wireless Sensor Networks
Edoardo Regini, Daeseob Lim, and Tajana Šimuni? Rosing
J. Low Power Electron. 7, 123-140 (2011)
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Instruction-Based Voltage Scaling for Power Reduction in SIMD MPSoCs
Sohaib Majzoub
J. Low Power Electron. 7, 141-147 (2011)
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Power-Gated Arithmetic Circuits for Energy-Precision Tradeoffs in Mobile Graphics Processing Units
Jeff Pool, Anselmo Lastra, and Montek Singh
J. Low Power Electron. 7, 148-162 (2011)
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Process Variation Tolerant FinFET Based Robust Low Power SRAM Cell Design at 32 nm Technology
Balwinder Raj, Jatin Mitra, Deepak Kumar Bihani, V. Rangharajan, A. K. Saxena, and S. Dasgupta
J. Low Power Electron. 7, 163-171 (2011)
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Hybrid Subthreshold and Nearthreshold Design Methodology for Energy Minimization
J. Kevin Hicks and D. Kudithipudi
J. Low Power Electron. 7, 172-184 (2011)
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Lower VDD Operation of FPGA-Based Digital Circuits Through Delay Modeling and Time Borrowing
J. Freijedo, M. D. Valdés, L. Costas, M. J. Moure, J. J. Rodríguez-Andina, J. Semião, F. Vargas, I. C. Teixeira, and
J. P. Teixeira
J. Low Power Electron. 7, 185-198 (2011)
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An Optimum Body Biasing for Gain and Linearity Control in CMOS Low-Noise Amplifiers
Aya Mabrouki, Thierry Taris, Yann Deval, and Jean-Baptiste Bégueret
J. Low Power Electron. 7, 199-208 (2011)
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Evaluation of Parasitic Components in LC Oscillators by Time-Varying Root-Locus
Svetozar S. Broussev and Nikolay T. Tchamov
J. Low Power Electron. 7, 209-217 (2011)
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Digital Sliding Mode Control of DC-DC Buck Converters
Bruno Jacinto, Carlos Moreira, and Marcelino Santos
J. Low Power Electron. 7, 218-233 (2011)
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Spintronic Memristor: Compact Model and Statistical Analysis
Miao Hu, Hai (Helen) Li, Yiran Chen, and Xiaobing Wang
J. Low Power Electron. 7, 234-244 (2011)
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Transparent-Segmented-Scan without the Routing Overhead of Segmented-Scan
Irith Pomeranz and Sudhakar M. Reddy
J. Low Power Electron. 7, 245-253 (2011)
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A SPECIAL SECTION
Selected Articles from the PATMOS 2010 Workshop
Guest Editor: Rene van Leuken
J. Low Power Electron. 7, 254 (2011)
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RESEARCH ARTICLES
An Automated Power Emulation Framework for Embedded Software-Detecting Power-Critical Code
Regions and Optimizing Software-Induced Power Consumption Peaks
Christian Bachmann, Andreas Genser, Christian Steger, Reinhold Weiß, and Josef Haid
J. Low Power Electron. 7, 255-264 (2011)
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On-line Power Optimization of Data Flow Multi-Core Architecture Based on Vdd-Hopping for Local
Dynamic Voltage and Frequency Scaling
Pascal Vivet, Edith Beigne, Hugo Lebreton, and Nacer-Eddine Zergainoh
J. Low Power Electron. 7, 265-273 (2011)
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Self-Timed SRAM for Energy Harvesting Systems
Abdullah Baz, Delong Shang, Fei Xia, and Alex Yakovlev
J. Low Power Electron. 7, 274-284 (2011)
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Optimal Logic Architecture and Supply Voltage Selection Method to Reduce the Impact of the Threshold Voltage
Variation on the Timing
Bahman Kheradmand-Boroujeni, Christian Piguet, and Yusuf Leblebici
J. Low Power Electron. 7, 285-293 (2011)
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Low Power Multiple-Value Voltage-Mode Look-Up Table for Quaternary Field Programmable Gate Arrays
Cristiano Lazzari, Jorge Fernandes, Paulo Flores, and José Monteiro
J. Low Power Electron. 7, 294-301 (2011)
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A SPECIAL ISSUE
A Special Issue on Low Power Design and Verification Techniques
Guest Editor: Shireesh Verma
J. Low Power Electron. 7, 1 (2011)
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RESEARCH ARTICLES
A Multi-Processing Systems-on-Chip Native Simulation Framework for Power and Thermal-Aware Design
Daniel Calvo, Pablo González, Luís Díaz, Héctor Posadas, Pablo Sánchez, Eugenio Villar, Andrea Acquaviva, and
Enrico Macii
J. Low Power Electron. 7, 2-16 (2011)
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Dynamic Reconfiguration of Two-Level Cache Hierarchy in Real-Time Embedded Systems
Weixun Wang and Prabhat Mishra
J. Low Power Electron. 7, 17-28 (2011)
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Efficient Evaluation of Power/Area/Latency Design Trade-Offs for Coarse-Grained Reconfigurable Processor Arrays
Dmitrij Kissler, Frank Hannig, and Jürgen Teich
J. Low Power Electron. 7, 29-40 (2011)
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Power Management Design and Verification
Bhanu Kapoor and Shireesh Verma
J. Low Power Electron. 7, 41-48 (2011)
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Low-Power, Battery-Operated, Large-Bandwidth Analog Integrated DC/DC Step-Down Converters
Malal Bathily, Bruno Allard, Frederic Hasbani, and Vincent Pinon
J. Low Power Electron. 7, 49-60 (2011)
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Design Matrix Analysis for Capacitive Interpolation Flash ADC
He Tang, Hui Zhao, Siqiang Fan, Xin Wang, Lin Lin, Qiang Fang, Jian Liu, and Albert Wang
J. Low Power Electron. 7, 61-70 (2011)
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On-Chip Single-Inductor Multiple-Output Power Converter Design with Adaptive Cross Regulation and
Supply Variation Control for Power-Efficient VLSI Systems
Yi Zhang, Rajdeep Bondade, and Dongsheng Ma
J. Low Power Electron. 7, 71-86 (2011)
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Oxide-Tunneling Leakage Suppressed SRAM for Sub-65-nm Very Large Scale Integrated Circuits
Ji-Hye Bong, Kwan-Hee Jo, Kyeong-Sik Min, and Sung-Mo (Steve) Kang
J. Low Power Electron. 7, 87-95 (2011)
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A Bit-Interleaved 2-Port Subthreshold 6T SRAM Array with High Write-Ability and SNM-Free Read in 90 nm
Abhijit Sil and Magdy Bayoumi
J. Low Power Electron. 7, 96-109 (2011)
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Cyber-Physical Thermal Management of 3D Multi-Core Cache-Processor System with Microfluidic Cooling
Hanhua Qian, Xiwei Huang, Hao Yu, and Chip Hong Chang
J. Low Power Electron. 7, 110-121 (2011)
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